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Supported by:
University LSI Design Contest
The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovation and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed-Signal Circuits, (2) Digital Signal Processor, (3) Microprocessors, and (4) Custom Application Specific Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices.
This year, the University LSI Design Contest Committee received 7 designs from four countries/areas, and selected 6 designs out of them. The selected designs will be discussed in Session 1A at three-minute presentations, followed by interactive discussions in front of their posters. For one outstanding design, the Best Design Award will be awarded in the opening session. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please come to the University LSI Design Contest and enjoy the stimulating discussions.
- Date: Tuesday, January 14, 2020
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Place: China National Convention Center
- Oral Presentation: Room 310 (10:45-11:30)
- Poster Presentation: Room 310 (11:30-12:00)
- Co-chairs: Xiaoyang Zeng (Fudan University) and Shouyi Yin (Tsinghua University)
- University LSI design contest committee
- UDC Session Schedule (html-version)
| Title | |
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| 1A-1 | Design of a Single-Stage Wireless Charger with 92.3%-Peak-Efficiency for Portable Devices Applications |
| 1A-2 | A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 um CMOS |
| 1A-3 | A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR |
| 1A-4 | A Quantity Evaluation and Reconfiguration Mechanism for Signal- and Power-Interconnections in 3D-Stacking System |
| 1A-5 | An Inductively Coupled Wireless Bus for Chiplet-Based Systems |
| 1A-6 | FPGA-based Heterogeneous Solver for Three-Dimensional Routing |